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XM20C64 1 ?xicor, inc. 1991, 1995, 1996 patents pending characteristics subject to change without notice 3874-1.6 6/20/96 t0/c2/d0 ns high speed autostore ? novram 64k XM20C64 8k x 8 features ? high speed: t aa = 55ns ? no batteries!! ? low power cmos ? autostore ? novram automatically stores ram data to e 2 prom upon power-fail detection ? open drain autostore output pin provides interrupt or status information linkable to system reset circuitry ? auto recall automatically recalls e 2 prom data during power-on ? fully decoded module ? full military temperature range C55 c to +125 c ? high reliability endurance: 1,000,000 nonvolatile store cycles data retention: 100 years ? esd protection 3 2kv all pins ? also available in 66 pin puma package description the XM20C64 is a high speed nonvolatile ram module. it is comprised of four xicor x20c16 high speed novrams, a high speed decoder and decoupling capacitors mounted on a co-fired multilayered ceramic substrate. the XM20C64 is configured 8k x 8 and is fully decoded. the module is a 28-lead dip conforming to the industry standard pinout for srams. the XM20C64 fully supports the autostore feature, providing hands-off automatic storing of ram data into e 2 prom when v cc falls below the autostore threshold. the XM20C64 is a highly reliable memory component, supporting unlimited writes to ram, a minimum 1,000,000 store cycles and a minimum 100 year data retention. 3874 fhd f01 ne oe we ce a0Ca10 i/o ne oe we ce a0Ca10 i/o ne oe we ce a0Ca10 i/o ne oe we ce a0Ca10 i/o y0 y1 y2 y3 1 a1 a0 2 3 a12 a11 ce 7 autostore we oe ne a0Ca10 i/o0Ci/o7 6 5 4 23 31 25 2 30 23 31 25 2 30 23 31 25 2 30 23 31 25 2 30 autostore? novram is a trademark of xicor, inc. functional diagram pin configuration 3874 fhd f02.1 ne a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v cc we as a 8 a 9 a 11 oe a 10 ce i/o 7 i/o 6 i/o 5 i/0 4 i/o 3
XM20C64 2 pin descriptions addresses (a 0 -a 12 ) the address inputs select an 8-bit memory location during read and write operations. chip enable ( ce ce ce ce ce ) the chip enable input must be low to enable all read, write and user requested nonvolatile operations. output enable ( oe oe oe oe oe ) during normal ram operations oe controls the data output buffers. if a hardware nonvolatile operation is selected ( ne = ce = low) and oe strobes low, a recall operation will be initiated. oe low will always disable a store operation regard- less of the state of ne , we , and ce so long as the internal transfer has not commenced. write enable ( we we we we we ) during normal ram operations we = ce = low will cause data to be written to the ram address pointed to by the a 0 -a 12 inputs. nonvolatile enable ( ne ne ne ne ne ) the nonvolatile input controls the transfer of data from the e 2 prom array to the ram array, when strobed low in conjunction with ce = oe = low. data in/data out (i/o 0 -i/o 7 ) data is written to or read from the x20c64 through the i/o pins. the i/o pins are placed in the high impedance state when either ce or oe is high or when ne is low. autostore output ( as as as as as ) as is an open-drain output. when it is asserted (driving low) it indicates v cc has fallen below the autostore threshold and an internal store operation has been initiated. because as is an open drain output it may be wire-ored with multiple open drain outputs and used as an interrupt input to a microprocessor. device operation novram operations are identical to those of a standard sram. when oe and ce are asserted data is presented at the i/os from the address location pointed to by the a 0 Ca 12 inputs. ram write operations are initiated and the address input is latched by the high to low transition of ce or we , whichever occurs last. data is latched on the rising edge of either ce or we , whichever occurs first. an array recall, e 2 prom data transferred to ram, is initiated whenever oe = ne = ce = low. a recall is also performed automatically upon power-up. command sequence operations the x20c64 employs a version of the industry standard software data protection (sdp). the end user can select various options for transferring data from ram into the e 2 prom array. all command sequences are comprised of three specific data/address write operations performed with ne low. a store operation can be directly selected by issuing a store command. the user may also enable and disable the autostore function through the software data protection sequence. refer to table 1 below for a complete description of the command sequence. operational notes the x20c64 should be viewed as a subsystem when writing software for the various store operations. the module contains four discrete components each need- ing to be set to the required state individually. the two high order address bits (a 11 and a 12 ) select only one of the four components.
XM20C64 3 table 1 step operation a 0 Ca 10 * data pattern 1 write 555 aa 2 write 2aa 55 3 write 555 command 3874 pgm t11 table 2 command function cc[h] enable autostore cd[h] disable autostore 33[h] store operation 3874 pgm t12.2 * it should be noted, the high order addresses should remain stable during the operations. it should also be noted that these commands are not global, that is only one device on the module will be affected by each command operation. command sequence note: all write command sequence timings must conform to the standard write timing requirements. command sequence timing limits limits symbol parameter min. max. units t sto store time 5 ms t sp command write pulse width 50 ns t sph inter command delay 55 ns 3874 pgm t01.1 3874 fhd f03.1 address 555 2aaa 555 oe ce we ne data in t sto t sp cmd 55 aa t dh t ds
XM20C64 4 d.c. operating characteristics (over recommended operating conditions unless otherwise specified.) limits symbol parameter min. max. units test conditions l cc1 v cc active current 100 ma ne = we + v ih , ce = oe = v il, address inputs = ttl inputs @ f = 20mhz all i/os = open i cc2 v cc active current 10 ma all inputs = v ih, all i/os = open (autostore) i sb v cc standby current 1.5 ma all inputs = v cc C0.3v all i/os = open i li input leakage current 10 m av in = v ss to v cc i lo output leakage current 10 m av in = v ss to v cc , ce = v ih v il (1) input low voltage C0.5 0.8 v v ih (1) input high voltage 2 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 5ma v olas autostore output 0.4 v i olas = 1ma voltage v oh output high voltage 2.4 v i oh = C4ma 3874 pgm t08.2 absolute maximum ratings* temperature under bias .................. C65 c to +125 c storage temperature ....................... C65 c to +125 c voltage on any pin with respect to v ss ............................................ C1v to +7v lead temperature (soldering, 10 seconds) .............................. 300 c *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the module. this is a stress rating only and the functional operation of the module at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect module reliability. supply voltage limits XM20C64 5v 10% 3874 pgm t07 recommended operating conditions temperature min. max. military C55 c +125 c 3874 pgm t06 capacitance t a = +25 c, f = 1mhz, v cc = 5v. symbol test max. units conditions c i/o (2) input/output capacitance 40 pf v i/o = 0v c in (2) input capacitance 24 pf v in = 0v 3874 pgm t10.1 power-up timing symbol parameter max. units t pur power-up (v cc min.) to ram operation 500 m s t pust power-up (v cc min.) to store operation 5 ms 3874 pgm t09 notes: (1) v il min. and v ih max. are for reference only and are not tested. (2) this parameter is periodically sampled and not 100% tested.
XM20C64 5 a.c. characteristics (over the recommended operating conditions unless otherwise specified) read cycle limits limits symbol parameter min. max. units t rc read cycle time 55 ns t ce chip enable access time 55 ns t aa address access time 55 ns t oe output enable access time 30 ns t lz (3) ce low to output in low z 0 ns t olz (3) oe low to output in low z 0 ns t hz (3) ce high to output in low z 0 25 ns t ohz (3) oe high to output in low z 0 25 ns t oh output hold 0 ns 3874 pgm t03 mode selection ce ce ce ce ce we we we we we ne ne ne ne ne oe oe oe oe oe mode i/o state power h x x x module not selected high z standby l h h l read ram active data output active l l h x write ram data input active l l l h issue software command data input active l h h h output disabled high z active l h l l hardware array recall high z active l h l h no operation high z active l l l l not allowed high z active 3874 pgm t04.1 read cycle timing diagram 3874 fhd f05 note: (3) t lz min., t hz min., t olz min., and t ohz min. are periodically sampled and not 100% tested. t hz max. and t ohz max. are measured from the point when ce or oe return high (whichever occurs first) to the time when the outputs are no longer driven. t ce t rc address ce oe t oe t lz t olz t oh t aa t hz t ohz i/o t oe
XM20C64 6 t wc t cw t as t wp t ds t dh t ow t wr data valid address oe ce we data out data in write cycle limits limits symbol parameter min. max. units t wc write cycle time 55 ns t wp we pulse width 40 ns t cw ce pulse width 40 ns t as address setup 0 ns t ds data setup 25 ns t dh data hold 0 ns t ow output active from end of write 5 ns t wr end of write to read 0 ns 3874 pgm t02 write cycle timing diagram 3874 fhd f04
XM20C64 7 array recall timing limits symbol parameter min. max. units t rcc array recall time 10 m s t rcp recall strobe pulse width 50 ns t rwe delay from we high to recall 0 ns 3874 pgm t05.1 note: the recall sequence must be repeated for each memory component individually. this is accomplished by sequencing through the array recall cycle with all four combinations of a 11 , and a 12 . array recall cycle 3874 fhd f06.1 equivalent test load circuit symbol table waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance address ne oe we ce data i/o t rcc t rcp t rwe 3874 fhd f07.2 735 w 318 w output 30pf 5v
XM20C64 8 pin configuration 3874 ill f10 i/o8 we2 i/o15 i/o9 ce2 i/o14 i/o10 gnd i/o13 as i/o11 i/o12 ne a10 oe nc nc nc nc nc we1 nc vcc i/o7 i/o0 ce1 i/o6 i/o1 nc i/o5 i/o2 i/o3 i/o4 i/o24 vcc i/o31 1 1223 344556 11 22 33 44 55 66 i/o25 ce4 i/o30 i/o26 we4 i/o29 a6 i/o27 i/o28 a7 a3 a0 a15 a4 a1 a8 a5 a2 a9 we3 i/o23 i/o16 ce3 i/o22 i/o17 gnd i/o21 i/o18 i/o19 i/o20 XM20C64p packaging information .100 typ .100 typ .600 typ .149+/-.015 .320 max .050 .164 .130 .410 1.09+/-.010 sq .040 .050 typ .180 3874 ill f11 all measurements in inches pin #1 identifier (not chamfered) 0.15 .018
XM20C64 9 1.600 max. (40.64) pin 1 1.300 .005 (33.02 0.13) tol. non. accum. .018 .002 (.46 .05) .100 .005 (2.54 .13) typ. .010 (.25) min. .295 (6.00) max. .140 (3.56) min. + .002 C .001 + .05 C .03 .010 (.25 ) .600 .010 (15.24 .25) 3926 fhd f40 28-pin dual-in-line package ceramic leadless chip carriers on ceramic sidebrazed ceramic substrate notes: 1. all dimensions in inches (in parentheses in millimeters) 2. dimensions with no tolerance for reference only .600 (15.24) .580 (14.73) packaging information
XM20C64 10 notes XM20C64p
XM20C64 11 ordering information XM20C64: 2k x 8 cmos novram memory module XM20C64 x x -x device access time C55 = 55ns temperature range blank = commercial = 0 c to +70 c i = industrial = C40 c to +85 c m = military = C55 c to +125 c mhr = military high rel blank = 28 lead ceramic dip module p = 66 pin puma module limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemnification provisions appearing in its terms of sale only. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. xicor, inc. makes no warranty of merchantability or fitness for any purpose. xicor, inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no other circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicor's products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
XM20C64 12 u.s. sales offices corporate office xicor inc. 1511 buckeye drive milpitas, ca 95035 phone: 408/432-8888 fax: 408/432-0640 e-mail: info@smtpgate.xicor.com northeast region xicor inc. 1344 main street waltham, ma 02154 phone: 617/899-5510 fax: 617/899-6808 e-mail: xicor-ne @smtpgate.xicor.com southeast region xicor inc. 100 e. sybelia ave. suite 355 maitland, fl 32751 phone: 407/740-8282 fax: 407/740-8602 e-mail: xicor-se @smtpgate.xicor.com southwest region xicor inc. 4100 newport place drive suite 710 newport beach, ca 92660 phone: 714/752-8700 fax: 714/752-8634 e-mail: xicor-sw @smtpgate.xicor.com northwest region xicor inc. 2700 augustine drive suite 219 santa clara, ca 95054 phone: 408/292-2011 fax: 408/980-9478 e-mail: xicor-nw @smtpgate.xicor.com mid-atlantic region xicor inc. 50 north street danbury, ct 06810 phone: 203/743-1701 fax: 203/794-9501 e-mail: xicor-ma @smtpgate.xicor.com north central region xicor inc. 810 south bartlett road suite 103 streamwood, il 60107 phone: 708/372-3200 fax: 708/372-3210 e-mail: xicor-nc @smtpgate.xicor.com south central region xicor inc. 11884 greenville ave. suite 102 dallas, tx 75243 phone: 214/669-2022 fax: 214/644-5835 e-mail: xicor-sc @smtpgate.xicor.com international sales offices singapore/malaysia/india xicor inc. 2700 augustine drive suite 219 santa clara, ca 95054 phone: 408/292-2011 fax: 408/980-9478 e-mail: xicor-nw @smtpgate.xicor.com korea xicor korea 27th fl., korea world trade ctr. 159, samsung-dong kangnam ku seoul 135-729 korea phone: (82) 2551.2750 fax: (82) 2551.2710 e-mail: xicor-ka @smtpgate.xicor.com ( ) = country code europe northern europe xicor ltd. grant thornton house witan way witney oxford ox8 6fe uk phone: (44) 1933.700544 fax: (44) 1933.700533 e-mail: xicor-uk @smtpgate.xicor.com central europe xicor gmbh technopark neukeferloh bretonischer ring 15 85630 grasbrunn bei muenchen germany phone: (49) 8946.10080 fax: (49) 8946.05472 e-mail: xicor-gm @smtpgate.xicor.com asia/pacific japan xicor japan k.k. suzuki building, 4th floor 1-6-8 shinjuku, shinjuku-ku tokyo 160, japan phone: (81) 3322.52004 fax: (81) 3322.52319 e-mail: xicor-jp @smtpgate.xicor.com mainland china taiwan/hong kong xicor inc. 4100 newport place drive suite 710 newport beach, ca 92660 phone: 714/752-8700 fax: 714/752-8634 e-mail: xicor-sw @smtpgate.xicor.com xicor, inc., marketing dept. 1511 buckeye drive, milpitas, california 95035-7493 tel 408/432-8888 fax 408/432-0640 rev. 4 3/96 stock# xx-x-xxxx xicor product information is available at: http://www.xicor.com

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